FIG. 1 shows a block diagram of an electronic system 100 having a plurality of masters sharing access to a memory device. Referring to FIG. 1, a plurality of masters including a first master 102, a second master 104, and a third master 106 share access to a multi-port memory device 108 which may be a multi-port SDRAM (synchronous dynamic random access memory). One of ordinary skill in the art is familiar with a SDRAM that operates synchronously with a clock signal from a master. In addition, a SDRAM is a command-based memory device with a master indicating a command by setting the logic states of a plurality of control signals.
The SDRAM 108 is deemed multi-port because the SDRAM 108 has a plurality of ports including a first port 112, a second port 114, and a third port 116. Each of the first, second, and third ports 112, 114, and 116 has a respective established signal interface SIF1, SIF2, or SIF3 for communication with a respective controller 122, 124, or 126 of the respective master 102, 104, or 106. Each of the signal interfaces SIF1, SIF2, and SIF3 is used for communication of control signals and data between the respective master 102, 104, or 106 and the SDRAM 108.
In addition, the first, second, and third masters 102, 104, and 106 have first, second, and third CPUs (central processing units), 132, 134, and 136, respectively. By running arbitration software, the CPUs 132, 134, and 136 arbitrate access to the shared SDRAM 108 among the masters 102, 104, and 106. The masters 152, 154, and 156 communicate such arbitration amongst them-selves via UART (universal asynchronous receiver/transmitter) interfaces 142 and 144. Generally, one of the masters 102, 104, and 106 is granted access for reading from or writing to the SDRAM 108 at a time.
FIG. 2 shows a timing diagram for arbitration between the first and second masters 102 and 104 for example. A first access indication signal SGM1 being set to the logical high state indicates that the first master 102 has access to the SDRAM 108, and the first master 102 is denied access when the first access indication signal SGM1 is set to the logical low state.
A second access indication signal SGM2 being set to the logical high state indicates that the second master 104 has access to the SDRAM 108, and the second master 104 is denied access when the second access indication signal SGM2 is set to the logical low state. In the example of FIG. 2, the first master 102 has access (i.e., has ownership) to the SDRAM 108 before time point T1, and the second master 104 has access to the SDRAM 108 after the time point T1.
Referring to FIG. 2, M1_CMD illustrates the commands generated by the first master 102, and M2_CMD illustrates the commands generated by the second master 104. In general, any command generated by a master is executed by the SDRAM 108 when that master has access. Otherwise, a command generated by a master not having access is not executed by the SDRAM 108. Thus in the example of FIG. 2, the SDRAM 108 performs the commands from the first master 102 before the time point T1 and from the second master 104 after the time point T1.
Thus, the SDRAM 108 executes active commands Active 1 and Active 12 each generated after a row cycle time tRC from periodic auto-refresh commands, as sent from the first master 102 before the time point T1. Each of the masters 102 and 104 periodically generates an auto-refresh command (as indicated by the lines labeled “Auto-Refresh” in FIG. 2).
Note that the first master 102 does not generate any active commands after time point T1 since the first master 102 is denied access. The first master 102 does generate the periodic auto-refresh commands after time point T1, but such auto-refresh commands are not executed by the SDRAM 108 after time point T1 (as indicated by the non-arrowed lines for the auto-refresh command after time point T1 in FIG. 2).
Further referring to FIG. 2, the SDRAM 108 executes active commands Active21 and Active22 each generated between the periodic auto-refresh commands, as sent from the second master 104 after the time point T1. In general, the row cycle time tRC is desired for the SDRAM 108 to execute the auto-refresh command before the SDRAM 108 may begin execution of an active command.
However in FIG. 2, a last auto-refresh command 152 from the first master 102 is being executed when the second master 104 sends the active command Active21 upon change of ownership at the time point T I. The active command Active21 is sent from the second master 104 before the end of the row cycle time tRC from the last auto-refresh command 152 resulting in “collision” of the Active21 command with the last auto-refresh command 152. As a result, the SDRAM 108 does not execute the Active21 command from the second master 104 upon change of ownership.
FIG. 3 shows another timing diagram of example signals SGM1, M1_CMD, SGM2, and M2_CM1 that results in “refresh starvation” in the SDRAM 108. The SGM1 and SGM2 signals in FIG. 3 illustrate frequent switching of ownership between the first and second masters 102 and 104. The first master 102 generates a series of active commands Active 11, Active 12, and Active 13 each between the periodic auto-refresh commands, and the second master 104 generates a series of active commands Active21, Active22, and Active23 each between the periodic auto-refresh commands.
However, only the active commands are generated within the times when the first and second masters 102 and 104 have access to the SDRAM 108. The auto-refresh commands are generated when the first and second masters 102 and 104 do not have access to the SDRAM 108. Thus, the SDRAM 108 only executes the active commands Active 11, Active21, Active 12, Active22, Active 13, and Active23, and does not execute any auto-refresh commands. The SDRAM 108 may operate improperly with such lack of execution of auto-refresh commands.
FIG. 4 shows another timing diagram of example signals SGM1, M1_CMD, SGM2, and M2_CMD that results in a “missing pre-charge” operation in the SDRAM 108. When the first master 102 has access with the SGM1 signal being set to the logical high state, the first master 102 issues a burst-read operation to the SDRAM 108 with a RAS (row address strobe) command followed by eight read commands RD1, RD2, RD3, RD4, RD5, RD6, RD7, and RD8.
However, a first change of ownership occurs at time point T1 in FIG. 4 to the second master 104 which then performs a write operation with a RAS command followed by a write command WR1. Such a first change of ownership at the time point T1 occurs after the first master 102 has issued the first four read commands RD1, RD2, RD3, and RD4. A second change of ownership occurs at time point T2 in FIG. 4 back to the first master 102 which then issues the rest of the four read commands RD5, RD6, RD7, and RD8.
A pre-charge of bit-lines in the SDRAM 108 is desired before the WR1 command issued by the second master 104 between the time points T1 and T2 in FIG. 4. However, such a desired pre-charge operation is missing in FIG. 4 because of the abrupt change of ownership at time point T1.
Thus, such disadvantageous features of collision of commands as illustrated in FIG. 2, refresh starvation as illustrated in FIG. 3, and a missing pre-charge operation as illustrated in FIG. 4 are desired to be prevented during arbitration by software amongst the masters 102, 104, and 106 for the shared SDRAM 108.